basic amplifier cell
3 terminal active device
one leg to ground, one gate controller, one attached to resistor to D.C.
the only difference between types is operating characteristics
NPN BJT, common emitter: signal on base, resistor to DC on collector, emitter on ground
2 things are important
DC part: have to set operation in static condition, set by Vce and Ic
Vce vs Ic graph looks like several capacitor charging curves describing Ib
KVL: Vce + IcRc - Vcc = 0 -> Ic = -Vce/Rc + Vcc/Rc
load line has negative slop, goes from (0,Vcc/Rc) to (Vcc,0)
operating point chosen on load line is called quiescent point, static point, q-point
for BJTs, base current of 0 is cutoff, left of the curves is saturation, amplification takes place in the active region
AC part: 
using a 2uApp base input signal, look at curve, qpoint moves along load line to vary Vce based on base input
too high or too low Ib can cause clipping in the cutoff or saturation region
you can only get so much amplification out of a BJT
to get more, you can use multiple amplifier stages
problem, have to deal with multiple input/output impedances

multistage amps: need to match impedance between stages, R1o == R2i, R2o == R3i, etc..., R6o == Rload
use interstage between stages and between last stage and load to adjust to the proper impedance, usually use common collector or common base for matching stages
common emitter allows delivery of LOTS of power to the load, ditto for common source in MOSFETs

common base: Vcb vs Ic with multiple lines of Ie, starts at Vcb<0, very hard to saturate since saturation is negative voltage
2 ways to get chart, use a curve tracer, setup experiment to determine curves (long way)
CE: small base current controls large collector current
CC: Vce vs Ie, Ib curves, not good at power delivery, good at matching resistances as interstage
CB: 

watch out for VT (termal voltage) = kT/q
as temp goes up, collector current drops, same for Ie and Ib
biggest enemy is heat

purpose of biasing
set desired operating region of the device, active region/saturation/cutoff
set q-point within the transistor's available design space
stabilize the qpoint from outside variations (DC supply level, variations in beta of BJT, variations in ambient temp)
no stable q-point means no control of circuit performance, 2 kinds of bias approaches:
	good techniques
	bad technique (widely used today)

Pcmax = Vce*Ic = constant q-point, but not max of both
have to operate in a region bounded by Pcmax hyperbolic curve, saturation region, and cutoff
load line does crazy things if temperature is increased and can bend or may burn up the transistor
slap a big ole heat sink on that bad boy

lousy techniques: single bias resistor with one DC source
good techniques: voltage divider with one DC source and emitter resistor
		Rth is R1 and R2 parallel, Vth is R2/(R1+R2), have to pick high Vth and high Re to swamp out other terms so Ic ~ Vth/Re
	voltage divider with two DC sources and emitter resistor
	constant current source (current mirror)