an example!
assumptions: q3,4 matched, pmos
q1,2 matched, nmos
Vtn = 1V = abs(Vtp)

DC analysis
Id1 = I/2 = Id2 = Id3 = Id4
KVL yields Vo+Vsd4-Vdd = 0 -> Vo = Vdd-Vsd4

saturation:
involving Vds, Vsd pmos
Idp = uCoxVwVw/2 * (1+Vsd/Va) -> Vsd3 = Vsd4

note from mirror: Vsg3 = Vsg4
using graphs, Id4 = Id3 = I/2, Vsg3 = Vsg4, thus Vsd3 = Vsd4

Vo = Vdd - Vsd4 = Vdd - Vsd3

for Q1,Q2
I/2 = Id = uCoxW/2L * (Vgs-Vtn)^2 -> Vgs1 = Vgs2
for Q3,Q4
I/2 = Id = uCoxW/2L * (Vsg-Vtp)^2 -> Vsg3 = Vsg4

signal part:
KCL io = id4-id2
KVL vds1+vgs3=0 -> vds1=-vgs3

from mirror circuitry: vsg3 = vsg4 -> vds1=-vsg4

id = (vsd4/ro4 + gm4*vsg4) - (vds2/ro2 + gm2*vgs2)
vsd4 = -ro1ro4gm1gm4vid/2
vds2 = ro2gm2vid/2